The present invention relates to the field of digital circuitry and programmable logic devices. More particularly, it relates to an input/output element circuit in a logic device where the input/output element circuit is suitable for interfacing with circuits or devices that use high speed input/output standards, such as memory using the double data rate and zero bus turnaround input/output standards.
Programmable logic devices (PLDs) are integrated circuit devices containing a number of logic elements that can be selectively programmed to implement a wide variety of logic circuit designs. PLDs are commonly used in digital electronic systems together with other devices such as processors, bus drivers, and memory devices. For example, a field programmable gate array (FPGA) is a PLD that contains an array of logic blocks that represent the individual elements of the logic circuit design being implemented. Each logic block is programmably configured and the blocks are programmably interconnected to implement a user""s desired logic functions and circuit design. Similarly, a complex PLD (CPLD) has a limited number of relatively large, user-programmable logic blocksxe2x80x94each of which is similar to a small PLDxe2x80x94that communicate with each other across an interconnect matrix.
In a PLD, input/output (I/O) terminals are used to provide data, control, address and clock signals to and from the configured logic blocks in the device. For example, memory controller logic blocks in FPGAs and CPLDs commonly read to and write from memory such as synchronous dynamic random access memory (SDRAM) or static random access memory (SRAM). The memory may be on the same integrated circuit device as the PLD or on a separate device. As used herein, an xe2x80x9cI/O terminalxe2x80x9d may refer to a terminal that is used as a unidirectional input terminal, exclusively as a unidirectional output terminal, or as a bidirectional terminal that can be configured to act either as an input or an output terminal at any one time. Since the size of a PLD circuit design depends on the number of logic blocks and the number of I/O terminals available, the use of bidirectional I/O terminals is often desirable to permit a given number of logic blocks to be implemented in smaller-sized device. Typically, the I/O terminals are physically implemented in an integrated circuit device as pins, pads, balls or some other type of terminal structure.
An I/O element circuit is often needed to provide an interface between an I/O terminal of a PLD logic array and an external device (or circuit) such as memory. The requirements of an I/O element circuit depend on the type of I/O terminal (i.e., input, output, or bidirectional) and on the I/O standard being used to communicate. Generally, a separate I/O element circuit is associated with each I/O terminal of the PLD. For bidirectional I/O terminals capable of being used for both reads and writes, the I/O element circuit typically provides an output enable (OE) signal that acts to selectively enable/disable write operations via the terminal. I/O element circuits, also referred to as I/O cells, can be programmably implemented as functional logic blocks, similar to the blocks in a PLD logic array.
Two I/O standards in particular, double data rate (DDR) and zero bus turnaround (ZBT), are frequently used in high speed data transfer applications. In the DDR I/O standard, data is clocked on both the rising and falling edge of a clock signal, effectively doubling the data rate of DDR SRAMs and SDRAMs. With the ZBT standard, synchronous fast SRAM devices are designed to provide 100% bus utilization by eliminating all idle clock cycles when turning the data bus around from a write operation to a read operation (or vice versa). This enables considerably faster operation in systems that require frequent and random read and write access, such as in networking and telecommunications applications.
In view of the above, there is a need for an I/O element circuit capable of allowing a logic device""s I/O terminal to operate in high speed data modes, especially a DDR I/O mode and a ZBT I/O mode. It would be particularly desirable if such an I/O element circuit were capable of being programmably configured to operate in the different I/O modes.
The present invention provides a programmable I/O element circuit for an I/O terminal of a logic array that is suitable for allowing the array to interface with, e.g., a memory device using high speed I/O modes such as DDR and ZBT I/O modes. The I/O element circuit includes an input block for unidirectional input I/O terminals, an output block for unidirectional output I/O terminals, and both input and output blocks for bidirectional I/O terminals. In one embodiment, the input block includes two input registers for registering input signals from the terminal at alternate clock edges. The output block may also include two output registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those registered output signals. For a bidirectional terminal, the multiplexer output is connectable to the I/O terminal via a gated output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays are optionally included in the input, output, and output enable paths. In particular, for ZBT modes, a programmable delay circuit in the output enable path may be used to provide a slower turn-on time than turn-off time for the output buffer, thereby avoiding the possibility of bus contention.
The I/O element circuit advantageously allows any regular I/O terminal in a logic array of a PLD or other logic device to be configured for a double data rate I/O standard using double edge clocking, and without increased clock to-output delays in the I/O element circuit in comparison to single data rate modes. This provides a flexible way of increasing system bandwidth without requiring a higher operating core frequency and helps reduce the board and packaging costs associated with a PLD. In addition, by also accommodating ZBT I/O modes, the programmable I/O element provides increased bandwidth at the same bus frequencies in applications that require a mixture of reads and writes.
Thus, the present invention provides a programmable I/O element circuit for an I/O terminal of a logic array that includes an input block, an output block and an output enable block. The input block includes a first input register having an input for receiving a signal at the I/O terminal and an output for registering the I/O terminal signal upon a first edge in an input clock signal. The output of the first input register is connectable to the logic array, e.g., via a programmable multiplexer. The input block also includes a second input register having an input for receiving the I/O terminal signal and an output for registering the I/O terminal signal upon a second edge in the input clock signal. The output of the second input register can also be coupled to the logic array, e.g., again via a programmable multiplexer. Alternatively, the input block includes an input bistable circuit having an input for receiving the registered I/O terminal signal output by the second input register and an output for latching the registered I/O terminal signal upon the first edge in the input clock signal. In this case, the output of the bistable circuit is connectable to the logic array.
The output block circuit includes a first output register having an input for receiving a first output signal from the logic array and an output for registering the first output signal upon a first edge in an output clock signal. A second output register has an input which, in at least one mode of operation (in particular, a DDR mode), receives a second output signal from the logic array and an output for registering the second output signal upon the first edge in the output clock signal. The output block circuit may also include a multiplexer having a first input connected to the output of the first output register, a second input connected to the output of the second output register, an address input configurable to receive the output clock signal, and an output connectable to the I/O terminal via a gated output buffer. In one embodiment, the input clock signal and output clock signal are provided by different clock sources.
The output enable block circuit receives an enable signal from the logic array and provides an output enable signal to a gating input of the output buffer. The output enable block circuit may include a first output enable register having an input for receiving the enable signal from the logic array and an output for registering a first registered enable signal upon the first edge in the output clock signal. This block can also include a second output enable register having an input for receiving the registered enable signal from the first output enable register and having an output for registering a second registered enable signal upon a second edge in the output clock signal. A logic circuit, e.g., an OR gate, can provide a combined registered enable signal that is connectable as the output enable signal to the gating input of the gated output buffer.
In another embodiment, the present invention provides a programmable I/O element circuit for a bidirectional I/O terminal of a logic array which includes an input register, an output register, and an output enable circuit. The input register has an input for receiving a signal at the I/O terminal and an output for registering the I/O terminal signal upon a first edge in an input clock signal. The output of the first input register is connectable to the logic array. The output register has an input for receiving an output signal from the logic array and an output for registering the output signal upon a first edge in an output clock signal. The registered output signal is connectable to the I/O terminal via a gated output buffer. The output enable circuit receives an enable signal from the logic array and provides an output enable signal to a gating input of the gated output buffer via a programmable delay circuit, wherein the output enable signal provides a slower turn-on time than turn-off time for the gated output buffer. The programmable delay circuit may include a logic gate having first and second inputs and an output. The first logic gate input receives a signal input to the programmable delay circuit, the second logic gate input receives a delayed version of the signal input to the programmable delay circuit, and the output of the logic gate provides the output enable signal.